AMD Zen6 Rumors: Over 200 Cores L2/L3 Cache and HBM SKU Redesign

AMD Zen6 Rumors: Over 200 Cores L2/L3 Cache and HBM SKU Redesign

AMD Zen6 Rumors: Over 200 Cores L2/L3 Cache and HBM SKU Redesign.

The YouTube channel Moore’s Law is Dead (MLID) revealed in the latest video that the successor to AMD’s EPYC Turin CPU will use the Zen 5 core called “EPYC Venice”, and will follow up with the Zen 6 core.

While details are still murky considering the product isn’t expected to launch until well over 2025, it looks like MLID has early details on the codename, and AMD ‘s marketing has come up with the “Venice” for its next-generation EPYC lineup. “. Named after the capital of the Veneto region in northeastern Italy, the EPYC Venice series is expected to be a huge update for the server.

Details about the Zen 6 core are also shared in the video, but it is uncertain whether AMD will continue to use Zen’s naming rules after 2025. The server side should continue to use the EPYC naming scheme.

It is reported that the x86 architecture after Zen 6 or Zen 5 will take advantage of a very mixed core design method and can provide more than 200 cores (a conservative estimate), with rumors of up to 384 cores per socket.

There’s no mention of whether this CPU will be compatible with the SP5 platform, but it looks like Turin and its successor Zen 5C could be the last EPYC chips for the upcoming platform.

The SP5 socket will last until 2025, which is a good time frame to provide an update.

As for the upgrades to the architecture itself, the leaker also said that AMD is expected to completely redesign the L2 and L3 cache systems. There will also be major changes to the Infinity Cache architecture.

In addition, HBM will be the standard for most product lines, and this memory standard will play a huge role in the next generation of EPYC CPUs.

The on-board HBM hybrid design integrated in the EPYC can be used to scale the IPC with the same core count.

An interesting and key detail is that Tom also expects Zen 5-based EPYC products to be one of the first AMD EPYC server products to be designed with HBM, and EPYC Venice will be standardized across multiple SKUs.