Apple embedded CPU may be fully transferred to RISC-V architecture

Apple embedded CPU may be fully transferred to RISC-V architecture

Apple embedded CPU may be fully transferred to RISC-V architecture. 

RISC-V chip architecture may change the global chip competition landscape! Apple’s embedded core may be fully transferred to RISC-V architecture.

A few days ago, according to SemiAnalysis, Apple is moving its embedded core to the RISC-V architecture.

RISC-V is an open source instruction set architecture (ISA) based on the reduced instruction set (RISC) principles.

In 2010, the open source instruction set architecture RISC-V first appeared at the University of California, Berkeley, and the form of its open source architecture quickly attracted IBM, NXP, WeatherDigital, NVIDIA, Qualcomm, Samsung, Google, Huawei, Tesla and other major manufacturers to join.

In contrast to most instruction sets, the RISC-V instruction set is free to be used for any purpose, allowing anyone to design, manufacture and sell RISC-V chips and software.

While this is not the first open source instruction set, it is significant because its design makes it suitable for modern computing devices (such as warehouse-scale cloud computers, high-end mobile phones, and tiny embedded systems).

The designers considered performance and power efficiency in these applications.

The instruction set also has numerous supported software, which addresses the shortcomings common to the new instruction set.

Semianalysis analyst Dylan Patel said that even though many believe RISC-V lacks a software ecosystem, he stressed that RISC-V is fast becoming the new processor standard.

“Apple’s A15 chip has more than a dozen Arm-based CPU cores distributed for various non-user-facing functions. SemiAnalysis can confirm that these cores are actively being converted to RISC-V in future hardware generations.”

In addition to the main core, the current Apple M-series processors have a large number of embedded cores responsible for various workloads that are not related to the operating system, including Wi-Fi/Bluetooth, touchpad control, thunderbolt interfaces, and more. These embedded cores run their own firmware, powering the perimeter around the main core that runs the operating system.

Currently, most of these embedded cores are based on Arm’s Cortex-M series or lower-end Cortex-A series cores, for which Apple needs to pay a large licensing fee.

With the further development of Apple’s self-developed chips, the number of cores used in the follow-up will also increase accordingly, and the fees paid will also rise.

Apple could save a lot of money if the embedded core would be fully shifted to the RISC-V architecture.

Apple bets on RISC-V, and there are early signs

As early as last year, there was news of Apple’s embrace of RISC-V in the market.

In September last year, Apple posted a job posting saying that it was looking for a team of Vector and Numerics Group (VaNG) for its core operating system team who had a detailed understanding and experience of the RISC-V instruction set architecture (ISA) and ARM’s Neon vector ISA. Developer.

According to the job advertisement, the engineer will use “innovative RISC-V solutions and state-of-the-art programming” on Apple products.

Specifically, Apple wants future engineers to use the RISC-V instruction set and understand ARM.

At the time, analysts believed that the recruitment could only indicate that Apple was exploring the use of RISC-V, but it was unknown whether it would ultimately decide to adopt the open source technology and whether it would replace the existing chip architecture. At present, Apple’s embrace of RISC-V may be a foregone conclusion.

In fact, more and more manufacturers and developers have joined the RISC-V camp in recent years.

Recently, Jack Kang, senior director of SiFive, which provides the core of RISC-V, said, “In recent years, China’s growing interest in RISC-V has stimulated the popularity of the architecture. By 2025, there will be more than 60 billion RISC-V cores are integrated into the IC.”