Rambus world premiere PCIe 6.0 controller with 256GB/s bandwidth

Rambus world premiere PCIe 6.0 controller with 256GB/s bandwidth

Rambus world premiere PCIe 6.0 controller with 256GB/s bandwidth.

A few days ago, the PCI-SIG organization officially released the PCIe 6.0 standard specification , which is also the biggest change since the technology was born. Not only has the bandwidth continued to increase, but the underlying bones and functional characteristics have also undergone earth-shaking changes.

On January 26, Rambus released the world’s first controller fully compliant with PCIe 6.0, supporting all new features , mainly for high-performance computing, data center, artificial intelligence and machine learning, automotive, Internet of Things, defense, aerospace and other sophisticated fields.

The controller supports PCIe 6.0 64GT/s transmission data rate , x1 channel can bring 8GB/s one-way physical bandwidth (equivalent to PCIe 4.0 x4), x16 is up to 256GB/s, and two-way is 512GB/s.

Of course, the new PAM4 pulse modulation is also a must . The number of coding states is doubled to 4, which can carry a maximum frequency of 30GHz, and FEC (forward error correction) is added to correct signal errors and ensure data integrity.

Rambus’ world premiere PCIe 6.0 controller: the biggest change in history, 256GB/s bandwidth

Other new features:

– Supports fixed size FLIT (Flow Control Unit) to ensure high bandwidth efficiency

– Internal data channels are automatically adjusted based on maximum link speed and bandwidth (256/512/1024 bits) to optimize throughput

– Support endpoint, boot port, dual mode, switch port configuration

– Integrated IDE (full data encryption) to optimize performance, monitor and protect links against physical attacks

– Backward compatible with PCIe 5.0/4.0/3.1/3.0

Rambus didn’t say when the PCIe 6.0 controller will ship.

Information about PCI Express 6.0 from wiki

On 18 June 2019, PCI-SIG announced the development of PCI Express 6.0 specification. Bandwidth is expected to increase to 64 GT/s, yielding 128 GB/s in each direction in a 16-lane configuration, with a target release date of 2021.[87] The new standard uses 4-level pulse-amplitude modulation (PAM-4) with a low-latency forward error correction (FEC) in place of non-return-to-zero (NRZ) modulation.[88]

Unlike previous PCI Express versions, forward error correction is used to increase data integrity and PAM-4 is used as line code so that two bits are transferred per transfer.

With 64 GT/s data transfer rate (raw bit rate), up to 252 GB/s is possible in ×16 configuration.[87]

On 24 February 2020, the PCI Express 6.0 revision 0.5 specification (a “first draft” with all architectural aspects and requirements defined) was released.[89]

On 5 November 2020, the PCI Express 6.0 revision 0.7 specification (a “complete draft” with electrical specifications validated via test chips) was released.[90]

On 6 October 2021, the PCI Express 6.0 revision 0.9 specification (a “final draft”) was released.[91]

On 11 January 2022, PCI-SIG officially announced the release of the final PCI-Express 6.0 specification.[92]

PAM-4 coding results in a vastly higher bit error rate (BER) of 10−6 (vs. 10−12 previously), so in place of 128b/130b encoding, a 3-way interlaced forward error correction (FEC) is used in addition to cyclic redundancy check (CRC).

A fixed 256 byte Flow Control Unit (FLIT) block carries 242 bytes of data, which includes variable-sized transaction level packets (TLP) and data link layer payload (DLLP); remaining 14 bytes are reserved for 8-byte CRC and 6-byte FEC. [93][94] 3-way Gray code is used in PAM-4/FLIT mode to reduce error rate; the interface does not switch to NRZ and 128/130b encoding even when retraining to lower data rates.[95] [96]