The next step in the evolution of the Intel x86 instruction set: AVX10 and APX
The next step in the evolution of the Intel x86 instruction set: AVX10 and APX
The next step in the evolution of the Intel x86 instruction set: AVX10 and APX.
Intel Corp. is gearing up for what the company considers the “next big step” in the evolution of the original x86 instruction set architecture (ISA).
The Santa Clara company is expanding the register count for general-purpose x86 operations while introducing a new, all-encompassing vector instruction set based on the well-known AVX-512 ISA.
As explained on Intel’s official website for developers, the x86 architecture is now widely used in data centers, personal computers, and various other environments that require performance-oriented CPUs and heavy computing workloads.
The original x86 ISA, introduced in 1978 with the 8086 CPU, had only eight 16-bit general-purpose registers, which have since doubled in number and quadrupled in size.
Registers play a vital role in a CPU because they store bits of data that the processor is actively working on at any given moment.
Therefore, Intel Corporation regards Advanced Performance Extensions (APX) technology as an important development step of x86 ISA.
It extends the entire x86 instruction set, allowing access to more registers, and introducing new features to improve the overall performance of the CPU.
APX doubles the number of general-purpose x86 registers from 16 to 32, giving the compiler more room for data storage, according to Intel.
Compared to binaries compiled against the Intel x64 ISA “benchmark,” APX-compiled code has “10 percent fewer loads and more than 20 percent fewer stores,” the company explained.
Simply put, register access is faster and consumes “significantly less” dynamic power than complex load and store operations.
Increased efficiency may lead to higher performance levels in the next generation of Intel CPU models.
APX will also extend the x86 ISA’s conditional instruction set, which was first introduced in the Pentium Pro processor with the CMOV/SET instruction.
These instructions are widely used by today’s compilers, and APX appears to improve branch prediction on Intel CPUs.
According to Intel, programmers can take advantage of APX’s capabilities simply by recompiling the code, since no source code modifications are required.
APX once again demonstrates the benefits of “x86 Variable Length Instruction Encoding”, a new feature that enhances the entire ISA by making “incremental changes” to the underlying silicon to decode instructions in hardware.
In addition to APX, future generations of Intel CPUs will also include the new AVX10 ISA.
As explained in the official documentation, the technology is a new major implementation of the AVX-512 vector instruction set that Intel first proposed in 2013.
The new ISA will establish a “universal, fused vector instruction set” across all Intel CPU architectures, enabling it to be supported on all future processors, including high-performance cores (P-cores) and high-efficiency cores (E -cores).
Intel initially introduced support for AVX-512 vector instructions on its 12th-generation Core consumer CPUs, but those instructions were only available on the P-core unit, and were later accidentally disabled via a firmware microcode update.
The vector extensions to the x86 ISA have proven very popular among developers trying to emulate the complex architecture of modern game consoles such as the PlayStation 3 (RPCS3).
The AVX10 extension to the x86 ISA will support all previously introduced AVX (vector) instruction extensions, up to a maximum vector register length of 256 bits.
The initial AVX10 release (AVX10.1) does not contain any new instructions; its sole purpose is to facilitate the transition from AVX-512 to a proper, all-core compatible (P core, E core) AVX10 implementation (ie AVX10.2).
