Intel to Launch 288-Core “Clearwater Forest” CPU in First Half of 2026
Intel to Launch 288-Core “Clearwater Forest” CPU in First Half of 2026, Leveraging Foveros Direct 3D with 9μm Interconnects
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Intel to Launch 288-Core “Clearwater Forest” CPU in First Half of 2026, Leveraging Foveros Direct 3D with 9μm Interconnects
Intel announced on October 9, 2025, the technical details of “Clearwater Forest” (development codename), the successor to the Xeon 6 6700E (codename: Sierra Forest).
The company plans to launch the processor under the Xeon 6+ brand in the first half of next year.
High-Density Server CPU with 288 Darkmont E-Cores
Clearwater Forest will be a density-focused data center CPU featuring a total of 288 Darkmont E-cores. The processor employs a new advanced packaging technology called “Foveros Direct 3D,” which enables 3D stacking of CPU dies on top of active base dies. Intel intends to target applications where core count is critical, such as telecom carriers’ 5G core infrastructure servers.
The new processor succeeds the Xeon 6 6700E series, which was announced in May 2024. Intel’s data center CPU lineup currently consists of two categories: the P-core variants (Xeon 6 6900P and 6700P, codename: Granite Rapids) and the E-core variant (Xeon 6 6700E).
The existing Xeon 6 6700E series features 144 cores based on the “Crestmont” CPU core architecture (also used in Core Ultra Series 1’s E-cores), with 8-channel memory support and 300W TDP. While Intel initially announced plans for a 288-core “Xeon 6 6900E” with two compute tiles, this variant was ultimately limited to specific customers and never saw widespread availability.
Next-Generation Darkmont Architecture Delivers Performance Gains
Clearwater Forest adopts the “Darkmont” E-core architecture, which will also be featured in the next-generation Core Ultra processor, Panther Lake. Darkmont represents a two-generation leap from Crestmont, with significant architectural improvements including an expanded decoder (from 6-wide to 9-wide), increased integer ALUs (from 4 to 8), and enhanced floating-point ALUs (from 3 to 4). These changes result in substantial IPC (Instructions Per Clock) improvements.
With 288 Darkmont cores in a single package, Clearwater Forest offers both increased core count and improved per-core performance compared to its predecessor—a significant achievement given that the 288-core Sierra Forest variant never materialized as a mainstream product.
Innovative Foveros Direct 3D with 9μm Pitch Interconnects
Intel’s success in bringing Clearwater Forest to market stems from two key technologies: manufacturing the CPU dies using the cutting-edge Intel 18A process node and employing the new “Foveros Direct 3D” chiplet technology.
Each Clearwater Forest compute tile contains six clusters of Darkmont cores, with each cluster comprising four cores sharing a single L2 cache—totaling 24 cores per compute tile. Twelve of these 24-core compute tiles are implemented on the package using Intel’s chiplet technology.
Previous Intel data center CPUs relied on EMIB (Embedded Multi-die Interconnect Bridge) technology, which connects dies through bridges embedded within an interposer. This approach was used in 4th Gen Xeon SP (Sapphire Rapids), 5th Gen Xeon SP (Emerald Rapids), and the current Xeon 6 generation products including Granite Rapids and Sierra Forest.
Clearwater Forest combines both EMIB and Foveros Direct 3D technologies. The architecture features three base tiles mounted on a substrate using EMIB, with twelve compute tiles stacked on top using Foveros Direct 3D with extremely fine 9μm pitch interconnects.
Unlike the Foveros S technology used in client processors (Meteor Lake, Arrow Lake, Lunar Lake, and Panther Lake), which employs passive dies, Clearwater Forest’s base dies are active. Each base die contains four DDR5 memory controllers, 192MB of LLC (Last Level Cache), and EMIB connections to other base dies and I/O dies. Three base dies and two I/O dies are mounted on the substrate via EMIB, with four compute tiles stacked on each base die using Foveros Direct 3D.
The manufacturing utilizes different process nodes: compute dies are built on the latest Intel 18A, base dies on Intel 3 (the previous generation’s compute tile process), and I/O tiles on Intel 7. The I/O tiles are essentially the same as those used in the previous Xeon 6 generation, maintaining pin compatibility with the Xeon 6 6900P series that supports 12-channel memory.
Pin-Compatible with Granite Rapids, Launch Expected at MWC 2026
Incorporating Darkmont cores, Foveros Direct 3D, and Intel 18A technology, Clearwater Forest emerges as a highly competitive high-density CPU. The processor will carry the Xeon 6+ branding—Intel received numerous requests to maintain the Xeon 6 designation for socket-compatible products.
The announcement focused on technical overview, with specific SKU configurations and detailed specifications to be revealed at the official launch in the first half of 2026. Given that high-density processors typically target telecom carriers’ 5G core infrastructure, an announcement at Mobile World Congress (MWC) 2026 in early March seems likely.
