Did Jensen Huang Misread Huawei’s Tau Scaling Law? Why His TSMC Comparison May Miss the Point

In the span of forty-eight hours, the global semiconductor industry witnessed two sharply contrasting moments. On May 25, 2026, Huawei’s semiconductor chief He Tingbo took the stage at the IEEE International Symposium on Circuits and Systems in Shanghai to unveil the company’s Tau (τ) Scaling Law — a proposed industry-wide paradigm shift away from geometric transistor miniaturization toward system-level signal latency optimization. Three days later, Nvidia CEO Jensen Huang, speaking to reporters after a high-profile “trillion-dollar dinner” in Taipei with leading figures from Taiwan’s semiconductor industry, offered a swift and dismissive verdict.

“This is a breakthrough for Huawei, but it’s not a threat for TSMC,” Huang said, according to reports from Radio Taiwan International and other outlets covering the event. His argument: TSMC had been employing die stacking and advanced 3D packaging technologies for close to a decade, and these methods were already well understood by Taiwan. By implication, what Huawei was presenting as a breakthrough was territory TSMC had long since mapped.

It was a confident assessment. It was also, according to a growing chorus of technical analysts, based on a fundamental category error.

What Huawei Actually Announced

The Tau Scaling Law is not simply a 3D packaging initiative. He Tingbo framed it as a new optimization axis for the semiconductor industry — one that replaces the question “how small can we make a transistor?” with “how fast can we move information through a system?” The law’s core metric is signal transmission time, not transistor size. Its production expression is LogicFolding, a chip architecture already deployed across 381 chip designs over the past six years, and set to debut publicly in the Kirin 2026 SoC launching this autumn.

Huawei’s LogicFolding technology reorganizes traditional flat, two-dimensional circuit layouts into vertical three-dimensional stacks — not at the packaging level, but at the design level, down to the individual standard cell and logic gate. The company’s chief semiconductor scientist, Liao Heng, described the method as one that “very finely and carefully split the critical paths of logic circuits across multiple layers.” The result, Huawei claims, is a 50–80% reduction in critical path trace lengths, a corresponding cut in RC (resistance-capacitance) load, and a transistor density gain of approximately 53.5%, equivalent to roughly three years of traditional Moore’s Law scaling — all achieved without access to more advanced lithography nodes.

TSMC’s 3D Technologies: Genuinely Advanced, But a Different Problem

To be clear: TSMC’s advanced packaging portfolio is among the most sophisticated in the world. Its CoWoS (Chip-on-Wafer-on-Substrate) technology links high-bandwidth memory and logic dies side-by-side on a silicon interposer — the backbone of every current Nvidia GPU and AI accelerator shipment. Its SoIC (System on Integrated Chips) platform stacks separately manufactured dies vertically using hybrid bonding, with pitches that TSMC’s own roadmap targets tightening from six microns today toward 4.5 microns by 2029.

These are formidable capabilities. But they address a different engineering challenge. In CoWoS and SoIC, the fundamental unit is the die — an independently designed and manufactured chip that is then integrated with other chips at the packaging stage. Circuit design within each die remains conventional and two-dimensional. Optimization occurs after the chips exist, not during their creation.

Peking University’s School of Integrated Circuits formalized this distinction in research published shortly after Huawei’s announcement, coining the terms “true 3D” and “pseudo-3D.” In pseudo-3D technology — the category covering conventional chiplet assembly and TSMC-style 3D packaging — all standard cells within a functional module must be placed on the same die; cross-die splitting of logic is not architecturally possible. Optimization operates on each independent die in isolation, heavily reusing mature 2D EDA workflows. In true 3D technology, by contrast, the entire multi-layer stack is treated as a unified design space: logic can be distributed, split, and optimized freely across dies, and all design stages — placement, routing, timing closure — operate across the complete three-dimensional volume.

Peking University’s team has already built a prototype EDA tool tailored specifically to this model. Early tests on open-source circuit designs reported a 30% reduction in total internal wire length alongside improvements in both performance and thermal management compared to conventional 2D workflows — a meaningful validation of the architectural premise, though independent large-scale audits of Huawei’s own silicon claims remain pending.

The Timeline: Key Events

• ~2015–2016 TSMC begins deep investment in CoWoS and SoIC 3D packaging. These technologies mature over the following decade into the backbone of AI accelerator manufacturing.
• May 19–22, 2025 Jensen Huang largely concedes the Chinese AI chip market to Huawei in a CNBC interview, citing the impact of US export restrictions on Nvidia’s China business.
• May 25, 2026 He Tingbo unveils the Tau (τ) Scaling Law and LogicFolding architecture at ISCAS 2026 in Shanghai. Huawei targets 1.4nm-equivalent transistor density by 2031 and announces Kirin 2026 chips for autumn.
• May 27, 2026 Peking University’s School of Integrated Circuits publishes details of a prototype true-3D EDA tool built specifically for LogicFolding workflows.
• May 28, 2026 Jensen Huang, speaking after the “trillion-dollar dinner” in Taipei with TSMC and Taiwan supply chain executives, tells reporters that Huawei’s Tau Scaling Law represents a breakthrough for Huawei but no threat to TSMC, citing TSMC’s decade-long work in die stacking and 3D packaging.
• May 29, 2026 Technical analysts and industry researchers widely challenge the equivalence drawn between LogicFolding and TSMC’s packaging technologies, noting they operate at different levels of abstraction.

Why the Conflation Matters

Huang’s framing is understandable as a competitive narrative. His core claim — that TSMC’s advanced packaging is world-class and not threatened — is entirely true on its own merits. TSMC and Intel retain a commanding process node lead, and their hybrid bonding roadmaps are advancing on schedule. The current generation of AI accelerators, including Nvidia’s own products, depends entirely on TSMC’s CoWoS and packaging capabilities.

But the rhetorical move of equating LogicFolding with those packaging technologies collapses a meaningful distinction. One set of technologies makes better use of pre-designed chips after they are built. The other reimagines how chips are designed in the first place. The former is an integration problem; the latter is a design methodology problem. Conflating them — even in an offhand interview remark — obscures what Huawei is actually claiming to have done: produce a new architectural grammar for silicon, not merely a better assembly technique.

Futurum Research, in an independent analysis published shortly after the announcement, noted that while TSMC and Intel retain their process node advantage, Huawei’s claimed 1.5-micron LogicFolding pitch in production “reframes the packaging competition in ways the industry has not fully priced in.” Bernstein analysts offered a more skeptical view, pointing out that increasing stacked layers raises power density and thermal risk — genuine engineering challenges that Huawei’s claims, still lacking independent audit, have yet to fully address at scale. Both assessments, notably, treat LogicFolding as a distinct category from traditional packaging rather than a subset of it.

The Bigger Picture: From Geometric to Systems Thinking

The Tau Scaling Law’s deepest ambition is precisely the one that makes Huang’s dismissal most incomplete. Huawei is not merely proposing a technique. It is proposing a new industry optimization target. Moore’s Law oriented the entire semiconductor industry around transistor geometry — shrinking the node, improving yield, advancing the lithography. The Tau Law proposes that the primary metric should instead be system-level signal transit time: how long it takes for information to move from origin to destination across the full hardware stack, from transistor switching through on-chip routing, inter-chip interconnect, memory access, and rack-level communication.

This is — at minimum — a coherent and non-trivial reframing. Whether the industry ultimately adopts it as an organizing principle, or whether Huawei’s specific implementations hold up under independent scrutiny at volume, remains to be seen. TSMC begins mass production of 1.4nm chips in 2028; if Huawei’s 2031 target holds, the manufacturing gap narrows from roughly five to seven years today to approximately three — a compressed differential, but a differential still.