Samsung SK Hynix & Micron LaunchDDR6 Development Race
Samsung SK Hynix & Micron Launch DDR6 Development Race
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Samsung, SK Hynix & Micron Launch
DDR6 Development Race
The world’s three largest memory makers have formally initiated R&D on the next generation of DDR memory, targeting speeds twice those of DDR5 and a commercial debut between 2028 and 2029 — driven almost entirely by AI data center demand.
Samsung, SK Hynix, and Micron — the trio that collectively controls the vast majority of global DRAM supply — have officially kicked off early-stage development work on DDR6 memory, marking the beginning of the industry’s next great memory transition. According to multiple substrate industry sources, the three manufacturers have already submitted preliminary design requests to their packaging and substrate partners, with initial test samples having entered the verification phase.
Technical Leap: Speed, Architecture & Signal Integrity
Current mainstream DDR5 modules top out at approximately 8.4 Gbps per pin. DDR6 is designed to double this, reaching a maximum of 17.6 Gbps with mature process technology — and potentially offering two to three times the total system throughput when architectural improvements are factored in. The new standard adopts a four-subchannel-per-module layout using 24-bit subchannels (replacing DDR5’s two 32-bit channels), which reduces per-channel electrical loading and sharpens signal integrity at extreme speeds.
That signal integrity challenge is precisely why memory makers are engaging substrate partners so early. As data rates climb, the electrical behaviour of the PCB substrate, trace geometries, and dielectric materials becomes critical. Engineers must control impedance mismatches, crosstalk, and on-die termination characteristics with far greater precision than previous generations demanded — a problem that cannot be solved by chip design alone.
“Memory manufacturers and substrate manufacturers typically begin joint R&D more than two years before a product’s official market launch. Early-stage R&D work on DDR6 has only recently officially begun.”
— Industry executive, cited by substrate supply chain sources, May 2026Standards Race: JEDEC & the Battle for Specification Control
The official DDR6 specification from JEDEC — the global body responsible for memory standards — remains a work in progress. A draft standard was circulated at the end of 2024, and the companion LPDDR6 mobile memory specification (JESD209-6) was formally ratified in July 2025. Final DDR6 ratification is broadly expected to occur during 2026, with CPU platform validation underway in parallel with both Intel and AMD.
For Samsung, SK Hynix, and Micron, participating actively in the standards process is as strategically important as the engineering itself. Manufacturers whose design proposals are incorporated into the final JEDEC specification gain first-mover advantages in optimisation and yield improvement — translating directly into cost and margin advantage when mass production begins.
The AI Engine Behind the Push
The urgency of DDR6 development is almost entirely attributable to artificial intelligence infrastructure. AI training and inference workloads are extraordinarily memory-bandwidth-intensive, and the server DRAM market has responded accordingly. According to data from market research firm TrendForce, DDR5’s share of server DRAM shipments exceeded 80% in 2025 and is forecast to reach 90% in 2026 — while DDR4’s share has collapsed below 20%, triggering serious industry discussion about phasing out DDR4 production entirely.
With DDR5’s generational transition now substantially complete, the major manufacturers are turning their attention to what comes next. AI data centers — where latency and bandwidth directly determine the cost of running large language models and training runs — will be the first beneficiaries of DDR6, before the standard filters down to consumer desktops and laptops.
A Generational Timeline in Context
Competitive Dynamics Among the Big Three
While Samsung, SK Hynix, and Micron are all pursuing DDR6, their starting positions differ. SK Hynix overtook Samsung in DRAM revenue for the first time in Q1 2025, powered by its dominant 53% share of the high-bandwidth memory (HBM) market. Samsung, whose HBM programme faced quality concerns before a recovery in late 2025, may have more pressure to assert leadership in conventional DDR standards. Micron, which holds roughly 11% of the HBM market and announced in December 2025 it was exiting the consumer memory segment entirely to focus on AI data centre customers, is arguably the most purely AI-aligned of the three going into the DDR6 era.
Prototype DDR6 chips have already been fabricated by all three manufacturers, and interoperability testing with memory controller vendors is underway. The race is not yet about who ships first — at this stage, it is about whose architectural choices become embedded in the final JEDEC standard, and who can demonstrate the most consistent yields when volume production eventually begins.
What to Watch
The next major milestone will be the final ratification of the DDR6 JEDEC specification, anticipated before the end of 2026. Following that, platform announcements from Intel and AMD confirming native DDR6 support in upcoming CPU generations will signal that the ecosystem is genuinely ready for commercialisation. For enterprises planning data centre investments, DDR6 is not an immediate purchasing consideration — but procurement teams and architects building infrastructure for 2028 and beyond should be factoring the new standard into their long-range planning today.
