The 432-core RISC-V chip has been taped out

The 432-core RISC-V chip has been taped out

The 432-core RISC-V chip has been taped out, with passive heat dissipation and low power consumption.

An Occamy processor , sponsored by the European Space Agency and developed by researchers at ETH Zurich and the University of Bologna, has been taped out.

The chip uses two sets of 32-bit 216-core RISC-V architecture chiplets (432 cores in total), plus an unknown number of 64-bit FPUs for matrix calculations, and two 16GB HBM2e memories from Micron (32GB in total).

The processor’s cores are interconnected through an intermediate layer and deliver 0.75 FP64 TFLOPS and 6 FP8 TFLOPS of computing power.

However, neither the European Space Agency nor its development partners have disclosed the power consumption of Occamy, although rumors suggest that the chip is passively cooled, which means it is a low-power processor.

Picture from pulp-platform.org

The chiplet design is one of the chip’s strengths, as it can include chiplets with other functions in subsequent packages to increase certain load capacities if necessary.

Occamy measures approximately 73 square millimeters, has a total of 1 billion transistors, and is built using GlobalFoundries’ 12nm process.

A 73 mm² chip isn’t a particularly large chip. For example, Intel’s Alder Lake uses a 10-nanometer process with a chip size of 163 square millimeters; Apple’s M2 processor uses a 5-nanometer process with a size of 217 square millimeters and 20 billion transistors.

The Occamy CPU was developed as part of the EuPilot initiative, which intends to develop homegrown processors to reduce reliance on proprietary x86 and ARM chips. It is also one of many chips that the European Space Agency is considering for spaceflight computing.

The feasibility will be verified based on this chip, and there is no guarantee that the chip will be 100% used in future space missions.

Reference:

https://pulp-platform.org/docs/date2023/2023-04-19-DATE-3DIC-workshop-v4-pulp-platform.pdf